Design Verification Engineer

WE’RE HIRING | Senior Design Verification Engineer 🇸🇪🔹 7+ Years ASIC/SoC Verification🔹 SystemVerilog + UVM🔹 UVM Testbench Development🔹 PCIe / AXI / VIP🔹 SVA & Functional Coverage🔹 Regression & Automation🔹 VCS / Verdi / Xcelium / Questa🔹 Python / Perl / Shell / Tcl🔹 Leadership & Mentoring📍 Sweden | Onsite 5 Days📄 FTC – 1 Year | Renewable📩 DM me with your updated CV if interested to [email protected]