Analog Mixed-Signal Design Verification Engineer

Job Title: Analog / Mixed-Signal (AMS) Design Verification Engineer – ContractLocation: Remote (Ideally Europe-based / CET ± 2 hours)Contract Type: Freelance / B2B ContractorStart Date: Late December / Early JanuaryDuration: 6–12 months (with option to extend) Required Experience & SkillsExperience: 5+ years in AMS Design Verification for complex ICs (e.g., ADCs, DACs, PLLs, PMICs).Languages & Modeling: SystemVerilog (including SV-RNM) and Verilog-AMS.Methodologies: UVM, constrained-random testing, functional coverage, and SVA.EDA Tools: Cadence (Xcelium/Virtuoso AMS), Synopsys (VCS/AMS), or Siemens (Questa/ADMS).Co-Simulation: Hands-on experience integrating SPICE views into digital UVM testbenches and debugging mixed-signal boundaries.Scripting: Python, Tcl, or Bash for testbench automation.