Senior ASIC / SoC Verification Engineer

Senior ASIC / SoC Verification Engineer | SystemVerilog & UVM We are looking for a Senior ASIC/SoC Verification Engineer with strong hands-on experience building verification environments from scratch. The assignment combines deep technical verification work with collaboration, mentoring, and contribution to verification best practices. Location: Lund, Sweden Mode of work: Remote (with monthly visit to Lund, Sweden)Contract Duration: 6 months + extensions Key ResponsibilitiesDevelop SystemVerilog/UVM tests and test benches from scratch.Build and enhance UVM components including drivers, monitors, scoreboards, and sequences.Develop, maintain, and integrate Verification IPs (VIPs).Implement SystemVerilog Assertions (SVA).Develop functional/code coverage and drive coverage closure.Maintain and improve existing verification environments.Support verification methodology, mentoring, onboarding, and technical collaboration. Key RequirementsSenior-level ASIC/SoC verification experience.Strong hands-on SystemVerilog and UVM expertise.Proven experience developing tests and complete test benches from scratch.Experience developing/integrating VIPs.Strong SVA, functional coverage, code coverage, and coverage analysis experience.Solid digital design/verification knowledge and Linux experience.Strong communication and cross-functional collaboration skills. Meriting: Telecom/networking/high-speed interface ASICs, regression/CI environments, mentoring, and experience in large R&D organizations.